Experience – Ingenieurbüro Lerch

Dresden area, Munich

since 7/2023 :

Development of regulators with the technologies from TSMC and UMC in 12nm to 28nm structre width with FinFETs and MOSFets in the voltage range up to 8V for different non volatile memories.

9/2018 – 6/2023 : Principal Engineer eNV-Memory Development, Compiler Competence Center

Team leader of „Compiler Competence Center“ with four additional members.
Development of a macro block generator (compiler) for Non volatile Memories, implementation of wider flexibility
Customer support for eNVM projects for the Non-Volatile-SRAM
Mixed signal post layout simulation of embedded non volatile memories with charge pumps and the implementation of macro model for unknown components.
Realization of a test chip concept to test multiple NVM IPs.
Data Mining and results analsis of qualification data from different non volatile IPs.
Failure analysis of field returns.

6/2016-9/2018 : Principal Engineer eNV-Memory Development, eNVM Design Center Dresden

Team leader of „NVM Design Dresden“ with seven additional members. The group was split 2018 into „Compiler Competence Centre“ and NVM Design
Development of customer specific Non-Volatile macro blocks based on a Non-volatile SRAM.
Supervision of the qualification of compiler generated macro blocks of NVSRAM and EEPROM.
Customer contact to define specification, test and qualification including the ramp up with the customer.
Supervision of projects regarding content and schedule of realization.

3/2011-5/2016 : Senior Engineer NV-Memory Development

Development of singe trim cell memory based on floating gate principle, including read amplifier and output driver for a 0.35µm standard CMOS technology.
Development of a charge pump to erase and program a non volatile memory in a 0.18µm standard CMOS technology with voltages +/- 15V
System modeling of a memory matrix and charge pump for a failure search and a ROM code implementation.
Creation of development specification and test specification
Simulation of developed blocks with analogue or mixed signal simulators. (spectre, AMS)
Creation of time continue replacement models for memory cells based on measurement results (Language:VerilogAMS).
Creation of a time discrete model of building blocks for a system observation (Language: Verilog)
Development of test fields for characterization purposes of single cells and complete building blocks for qualification. (Cadence Virtuoso)
Pattern generation for measurement.
Data mining of measurement results for characterization and qualification.
Automatic generation of documents.

12/2008 – 2/2011 : Senior Engineer PDK Development

Creating a PDK for 1.0μm technology for 650V with scripts to support the high-voltage design. The PDK contains symbols to create schematics, the simulator interface, parameterize able layout cells (pCells) and the data ex and import.
Creating Cadence PDK a 0.18μm technology and its different derivatives.
Creating Cadence PDK a 0.13μm technology.
PDK-update cycle, 2-3 PDKs per month.
Fully automated preparation of the PDK documentation
Quality assurance of the PDK’s with this self-developed software package using a LSF cluster.
Establishing a company-wide bug tracking solution based on Bugzilla
Development of an Assura Runset for detection of parasitic high voltage field effect transistors.

1/2007-11/2008 : Design Engineer Design Basics

Construction of a software package for creating Pcells for different technologies. The package now works with various sizes from 1.0 to 0.13 micron technologies and different voltage classes. Scope of typical elements of a technology is about 50 cells.

1/2006-12/2006 : Engineer Design Support

Programming of a software package for managing and producing the development kits (PDK) for customers to use ZMD’s own 0.6μm technologies.
Programming layout macro cells (Pcell) for in-house 0.6μm technology.

1/2004-12/2005 : Engineer Test Support and DfT

By outsourcing of the manufacturing, change to ‚ZMD AMMS GmbH & Co KG‘ (Z-Foundry) in Dresden. Work in the research project ‚Fault diagnosis of analog circuits‘ in collaboration with the ‚Fraunhofer Institut für Integrierte Schaltkreise‘ in Dresden (Test Engineer Support and DfT). [4-6]
Work in the research project ‚Reuse of Test Blocks‘ to automatically generate test patterns for analog circuits in cooperation with the Test House ‚Rood‘ in Nördlingen.

7/2002-12/2003 : Design Engineer

Establishing and maintaining an analog IP database and design of mixed signal circuits.

10/2001-6/2002 : RF Design Engineer

Development engineer in the ‚ZMD AG‘ in Dresden with the work area of development of an RF transmitter power amplifier for 900MHz [3].

9/2000-9/2001 Circuit Designer for Mixed-Signal Design

Test field development for the extraction of RF CMOS models in a 0.6μm technology

4/2000-8/2000 Thesis

Topic of the thesis: „Simulation und Modellierung von CMOS-Transistoren für HF-Anwendungen“, (Simulation and modeling of CMOS transistors for RF applications), Overall grade: „very good“ [4]

8/1998-6/2000 Student Assistant